 |
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
| Datasheet File OCR Text: |
| HT23B60 60 11 pixel data bank 8-bit mask mcu block diagram rev. 1.10 1 march 1, 2004 features operating voltage range: 2.4v~5.5v program rom: 32k 16 bits data ram: 2.3k 8 bits 16-bit table read instructions eight-level subroutine nesting timer two 16-bit programmable timer counters real time clock (rtc) watchdog timer (wdt) four operating modes: idle mode, sleep mode, green mode and normal mode built-in 32768hz x tal oscillator circuit build-in circuit dual system clock 32768hz, 3.58mhz build-in low battery detector 14 bidirectional i/o lines, 16 bidirectional i/o lines are share pin with segments lcd driver: up to a max. of 60 segments and 11 common 660 dots, 1/4 or 1/5 bias capability, 1/10 or 1/11 duty, r type lcd com/seg driving strength can be adjusted to compromise the display quality and current consumption, adjustable 16-level vlcd segment 0~15 supports key scan function build-in a serial-parallel-interface hardware circuit build-in a 8-bit pwm d/a hardware circuit 100-pin qfp package general description HT23B60 is an 8-bit cmos microcontroller with various functionalities in a compact package such as sram, rom i/os, interrupt controller, timer and lcd control - ler/driver. it s suitable for use as electrical data bank, lcd game, calendar and speech products. ! " ! # ! $ ! % ! & ! ' ! ( ! ) ' & ) ( % $ * + , - . . - / ) ( % $ * + , - / 0 1 " . - & & ( 2 - ! 1 " - 3 3 4 & 5 % 3 & 5 3 # 6 & 5 ' # ! - 7 - 8 $ & ' ' ' 1 " 9 - ' 1 # - 3 ' 1 ' & 9 - ' 1 ' ' - 1 3 ) ( ) : # * + , 1 " ) ( % $ * + , . ' . ( . ' . ( / ! 1 3 & ; - < / - 1 3 ( 1 3 ' 3 ) : # * + , < & ' = ' & 6 & 6 ' 6 # * 6 # = 6 pin assignment HT23B60 rev. 1.10 2 march 1, 2004 ' ( ) " # $ % * = ' & ' ' ' ( ' ) ' " ' # ' $ ' % ' * ' = ( & ( ' ( ( ( ) ( " ( # ( $ ( % ( * ( = ) & ) ' ) ( ) ) ) " ) # ) $ ) % ) * ) = " & " ' " ( " ) " " " # " $ " % " * " = # & * ' * ( * ) * " * # * $ * % * * * = = & = ' = ( = ) = " = # = $ = % = * = = ' & & * & % = % * % % % $ % # % " % ) % ( % ' % & $ = $ * $ % $ $ $ # $ " $ ) $ ( $ ' $ & # = # * # % # $ # # # " # ) # ( # ' 6 ) ( 6 ) ' 6 ) & 6 ( = 6 ( * 6 ( % 6 ( $ 6 ( # 6 ( " 6 ( ) 6 ( ( 6 ( ' 6 ( & 6 ' = 6 ' * 6 ' % 6 ' $ 6 ' # 6 ' " 6 ' ) 6 ' ( 6 ' ' 6 ' & 6 = 6 * 6 % 6 $ 6 # 6 " 6 ) < 6 3 & 1 ! 3 ' 1 3 ( 1 3 ) 1 3 " 3 # & ' ( ) " # $ % 6 & 6 ' 6 ( 6 # ) 6 # " 6 # # 6 # $ 6 # % 6 # * 6 # = & ' ( ) " # $ % * = ' & < 3 . ( . ' 6 # ( 6 # ' 6 # & 6 " = 6 " * 6 " % 6 " $ 6 " # 6 " " 6 " ) 6 " ( 6 " ' 6 " & 6 ) = 6 ) * 6 ) % 6 ) $ 6 ) # 6 ) " 6 ) ) pad assignment * the ic substrate should be connected to vss in the pcb layout artwork. HT23B60 rev. 1.10 3 march 1, 2004 ' ' & ( = = ' & ' ' & & > & 9 & ? = * = % = $ = # = " = ) = ( = ' = & * = * * * % * $ * # * " * ) * ( * ' * & % = % * % % % $ % # % " % ) % ( % ' % & $ = $ * $ % $ $ $ # $ " $ ) $ ( $ ' $ & # = # * # % # $ # # # " # ) # ( # ' ( ) " # $ % * = ' & ' ' ' ( ' ) ' " ' # ' $ ' % ' * ' = ( & ( ' ( ( ( ) ( " ( # ( $ ( % ( * ( = ) & ) ' ) ( ) ) ) " ) # ) $ ) % ) * ) = " & " ' " ( " ) " " " # " $ " % " * " = # & 6 ) 6 ( 6 ' % $ # " ) ( ' & 3 # 3 " 3 ) 1 3 ( 1 3 ' 1 3 & 1 ! 6 < < 6 & . ' . ( & 3 ' < ( ' & ) = " * % $ # " ) ( ' & 6 # = 6 # * 6 # % 6 # $ 6 # # 6 # " 6 # ) 6 # ( 6 # ' 6 # & 6 " = 6 " * 6 ) & 6 ) ' 6 ) ( 6 ) ) 6 ) " 6 ) # 6 ) $ 6 ) % 6 ) * 6 ) = 6 " & 6 " ' 6 " ( 6 " ) 6 " " 6 " # 6 " $ 6 " % 6 ( = 6 ( * 6 ( % 6 ( $ 6 ( # 6 ( " 6 ( ) 6 ( ( 6 ( ' 6 ( & 6 ' = 6 ' * 6 ' % 6 ' $ 6 ' # 6 ' " 6 ' ) 6 ' ( 6 ' ' 6 ' & 6 = 6 * 6 % 6 $ 6 # 6 " pad coordinates unit: m pad no. x y pad no. x y 1 1348.345 1337.600 52 1314.745 1252.900 2 1334.345 1076.850 53 1314.745 1152.900 3 1334.345 966.250 54 1314.745 1052.900 4 1334.345 866.250 55 1314.745 952.900 5 1330.600 746.150 56 1314.745 852.900 6 1330.600 635.550 57 1314.745 752.900 7 1330.600 535.550 58 1314.745 652.900 8 1330.600 424.950 59 1314.745 552.900 9 1330.600 324.950 60 1314.745 452.900 10 1330.600 214.350 61 1314.745 352.900 11 1330.600 114.350 62 1314.745 252.900 12 1330.600 3.750 63 1314.745 152.900 13 1330.600 96.250 64 1314.745 52.900 14 1330.600 206.850 65 1314.745 47.100 15 1330.600 306.850 66 1314.745 147.100 16 1330.600 417.450 67 1314.745 247.100 17 1330.600 517.450 68 1314.745 347.100 18 1330.600 628.050 69 1314.745 447.100 19 1330.600 729.826 70 1314.745 547.100 20 1323.500 863.400 71 1314.745 647.100 21 1282.800 970.900 72 1314.745 747.100 22 1323.500 1110.150 73 1314.745 847.100 23 1323.500 1305.950 74 1314.745 947.100 24 1191.900 1307.450 75 1314.745 1047.100 25 1083.800 1307.450 76 1314.745 1147.100 26 945.113 1293.950 77 1346.855 1319.590 27 835.109 1293.950 78 1246.855 1319.590 28 683.945 1217.385 79 1146.855 1319.590 29 519.280 1153.900 80 1046.855 1319.590 30 477.416 1321.600 81 946.855 1319.590 31 425.640 1153.900 82 846.855 1319.590 32 373.864 1321.600 83 746.855 1319.590 33 312.995 1153.860 84 646.855 1319.590 34 257.745 1320.790 85 546.855 1319.590 35 207.745 1153.861 86 446.855 1319.590 36 157.745 1320.790 87 346.855 1319.590 37 107.745 1153.821 88 246.855 1319.590 38 57.745 1320.790 89 146.855 1319.590 39 42.255 1320.790 90 46.855 1319.590 40 142.255 1320.790 91 84.745 1337.600 41 242.255 1320.790 92 184.745 1337.600 42 342.255 1320.790 93 295.345 1337.600 43 442.255 1320.790 94 395.345 1337.600 44 542.255 1320.790 95 505.945 1337.600 45 642.255 1320.790 96 605.945 1337.600 46 742.255 1320.790 97 716.545 1337.600 47 842.255 1320.790 98 816.545 1337.600 48 942.255 1320.790 99 927.145 1337.600 49 1042.255 1320.790 100 1027.145 1337.600 50 1142.255 1320.790 101 1137.745 1337.600 51 11314.745 1352.900 102 1237.745 1337.600 HT23B60 rev. 1.10 4 march 1, 2004 pad description pad no. pad name i/o mask option description 4~1 seg0~3 o selectable as lcd segment signal output or keyscan strobe signal. 12~5 pa0~pa7 i/o wake-up or none bidirectional 8-bit input/output port. each bit can be configured as wake-up input by mask option. software instructions determine the cmos output or schmitt trigger input with or without pull-high regis - ter by register [35h]. 14~13 pb4~pb5 i/o bidirectional 2-bit input/output port schmitt trigger input with or without pull-high register by software op - tion or cmos output 15 pb3/int i/o software instructions determine the bidirectional input/output pin or external interrupt schmitt trigger input or cmos output. when the [intc0].1 is set to 1 the pb3 will used to external interrupt input pin. for i/o pin: schmitt trigger input with or without pull-high register by software option or cmos output for int : edge trigger activated on a falling edge. 16 pb2/di i/o or i serial data input can be optioned as bidirectional input/output or serial data input. for i/o pin: schmitt trigger input or cmos output, see mask option table for pull-high function for serial data input: serial data input without pull-high resistor 17 pb1/do i/o or o serial data output can be optioned as bidirectional input/output or serial data output. for i/o pin: schmitt trigger input or cmos output, see mask option table for pull-high function for serial data output: sk is a cmos output 18 pb0/sclk i/o sclk signal can be optioned as bidirectional input/output or serial interface clock signal. for i/o pin: schmitt trigger input with or without pull-high resistor by register [36h] or cmos output for serial interface clock signal: use as serial i/o interface clock signal sclk should be set as serial clock output and after 8 clocks from the sclk terminal, clock output is automatically suspended. 19 res i schmitt trigger reset input. active low. 20, 21 vdd positive power supply 22, 23 vss negative power supply, ground 24 pwm1 o positive pwm cmos output 25 pwm2 o negative pwm cmos output 26 xout o a 32768hz crystal (or resonator) should be connected to this pin and xin 27 xin i a 32768hz crystal (or resonator) should be connected to this pin and xout 28 xc i external low pass filter used for frequency up conversion circuit 29 31 33 35 37 trim0 trim1 trim2 trim3 trim4 test pin only 30 lbin i this pin detects battery low through external r1/r2 to determine threshold, when the low voltage detect function is disabled, the lbin pin should be connected to vdd. 32 vlcd i lcd voltage input HT23B60 rev. 1.10 5 march 1, 2004 pad no. pad name i/o mask option description 46~38, 36 34 com0~8 com9 com10 o lcd common signal output 102~47 seg4~59 o lcd segment signal output absolute maximum ratings supply voltage ..........................v ss 0.3v to v ss +6.0v storage temperature ........................... 55 cto150 c input voltage ............................ v ss 0.5v to v dd +0.5v operating temperature .......................... 10 cto70 c current drain per pin excluding vdd and vss ........................................................................................... ........10ma note: these are stress ratings only. stresses exceeding the range specified under absolute maximum ratings may cause substantial damage to the device. functional operation of this device at other conditions beyond those listed in the specification is not implied and prolonged exposure to extreme conditions may affect device reliabil - ity. d.c. characteristics ta=25 c symbol parameter test conditions min. typ. max. unit v dd conditions v dd operating voltage 3v application 2.4 3.0 5.5 v i dd1 operating current (in normal mode) 3v 32768hz on, 3.58mhz on, cpu on, lcd on, wdt on, no load 1 1.5 ma i dd2 operating current (in green mode) 3v 32768hz on, 3.58mhz off cpu on, lcd off, wdt off, no load 815 a i stb1 standby current 1 (in sleep mode) 3v 32768hz on, 3.58mhz off, cpu off, lcd off, wdt off, no load 2.5 3 a i stb2 standby current 2 (in idle mode) 3v 32768hz off, 3.58mhz off, cpu off, lcd off, wdt off, no load 1 a v il input low voltage for i/o port 3v 0 1.0 v v ih input high voltage for i/o port 3v 2.0 v dd v v ol output low voltage 3v 0.4 v v oh output high voltage 3v 2.3 v dd v i ol1 i/o port sink current 3v v ol =0.3v 813 ma i oh1 i/o port source current 3v v oh =2.7v 4 8 ma i ol2 segment, common output sink current 3v v ol =0.3v 270 480 a i oh2 segment, common output source current 3v v oh =2.7v 100 140 a i ol3 pwm sink current 3v v ol =0.3v 16 26 ma i oh3 pwm source current 3v v oh =2.7v 16 26 ma r ph pull-high resistance of i/o ports 3v 30 60 90 k lbin low battery detection reference voltage 3v 1.10 1.15 1.20 v HT23B60 rev. 1.10 6 march 1, 2004 a.c. characteristics ta=25 c symbol parameter test conditions min. typ. max. unit v dd conditions f sys1 operating system clock (in green mode) 3v 32 khz f sys2 operating system clock (in normal mode) 3v 3.58 mhz t stb green mode to normal mode system frequency stable time 3v 20 ms t wdtosc1 watchdog oscillator period 3v 45 90 180 s t wdtosc2 watchdog time-out period (wdt osc) 3v without wdt prescaler 23 45 90 ms t wdt2 watchdog time-out period (system clock) 3v without wdt prescaler 512 t sys t wdt3 watchdog time-out period (32khz osc) 3v without wdt prescaler 15.6 ms t reset reset input pulse width 1 s t sst system start-up timer period 1024 t sys t int interrupt pulse width 1 s HT23B60 rev. 1.10 7 march 1, 2004 HT23B60 rev. 1.10 8 march 1, 2004 functional description execution flow the system clock for the HT23B60 is derived from a 32768hz crystal oscillator. a built-in frequency up con - version circuit provides dual system clock, namely 32768hz and 3.58mhz. the system clock is internally divided into four non-overlapping clocks. one instruc - tion cycle consists of four system clock cycles. instruction fetching and execution are pipelined in such a way that a fetch takes one instruction cycle while de - coding and execution takes the next instruction cycle. however, the pipelining scheme causes each instruc - tion to effectively execute within one cycle. if an instruc - tion changes the program counter, two cycles are required to complete the instruction. program counter pc the 13-bit program counter (pc) controls the sequence in which the instructions stored in program rom are ex - ecuted. after accessing a program memory word to fetch an in - struction code, the contents of the program counter are incremented by 1. the program counter then points to the memory word containing the next instruction code. when executing a jump instruction, conditional skip ex - ecution, loading pcl register, subroutine call, initial re - set, internal interrupt, external interrupt or return from subroutine, the pc manipulates the program transfer by loading the address corresponding to each instruction. ' ( ) " ' ( ) " ' ( ) " 4 - - > ? 6 @ - - > a ' ? 4 - > b ' ? 6 @ - > ? 4 - - > b ( ? 6 @ - - > b ' ? b ' b ( - / 0 ( - > - / ? 3 0 & 3 0 ' 3 0 ( * ' = ( ' $ - - - 3 & & & & + ' 4 4 4 + 0 3 0 - 3 $ 9 3 # - - ' " 9 ' ) - - 3 - - - 6 @ - - c - - / / - ) ( ! - - - - ' ) - 7 ( & & & + ) 4 4 4 + " & & & + # 4 4 4 + - 3 0 ) $ & & & + % 4 4 4 + - execution flow mode program rom address *14 *13 *12 *11 *10 *9 *8 *7 *6 *5 *4 *3 *2 *1 *0 initial reset 000000000000000 external or serial input interrupt 000000000000100 timer counter 0 overflow 000000000001000 timer counter 2 overflow 000000000001100 keyscan overflow 000000000010000 rtc overflow 000000000010100 pwm interrupt 000000000011000 skip pc+2 loading pcl *14 *13 *12 *11 *10 *9 *8 @7 @6 @5 @4 @3 @2 @1 @0 jump, call branch bp.6 bp.5 #12 #11 #10 #9 #8 #7 #6 #5 #4 #3 #2 #1 #0 return from subroutine s14 s13 s12 s11 s10 s9 s8 s7 s6 s5 s4 s3 s2 s1 s0 program rom address note: *14~*0: program rom address s14~s0: stack register bits @7~@0: pcl bits bp.5, bp.6: bit 5, 6 of bank pointer (04h) #12~#0: instruction code bits HT23B60 rev. 1.10 9 march 1, 2004 the conditional skip is activated by instruction. once the condition is met, the next instruction, fetched during the current instruction execution, is discarded and a dummy cycle takes its place while the correct instruction is ob - tained. the lower byte of the program counter (pcl) is a read/write register (06h). moving data into the pcl per - forms a short jump. the destination must be within 256 locations. when a control transfer takes place, an additional dummy cycle is required. program memory rom the program memory, which contains executable pro - gram instructions, data and table information, is com - posed of a 32768 16 bit format. however as the pc (program counter) is comprised of only 13 bits, the re - maining 2 rom address bits are managed by dividing the program memory into 4 banks, each bank having a range between 0000h and 1fffh. to move from the present rom bank to a different rom bank, the higher 2 bits of the rom address are set by the bp (bank pointer), while the remaining 13 bits of the pc are set in the usual way by executing the appropriate jump or call instruction. as the full 15 address bits are latched during the execution of a call or jump instruction, the correct value of the bp must first be setup before a jump or call is executed. when either a software or hardware inter- rupt is received, note that no matter which rom bank the program is in the program will always jump to the ap- propriate interrupt service address in bank 0. the origi- nal full 15 bit address will be stored on the stack and restored when the relevant ret/reti instruction is exe- cuted, automatically returning the program to the origi- nal rom bank. this eliminates the need for programmers to manage the bp when interrupts occur. certain locations in bank 0 of program memory are re - served for special usage: rom bank 0 (bp5~bp6=00b) the rom bank 0 ranges from 0000h to 1fffh. location 000h this area is reserved for the initialization program. af - ter a chip reset, the program always begins execution at location 000h. location 004h this area is reserved for the external interrupt or serial input interrupt service routine. if the int input pin is activated, and the interrupt is enabled and the stack is not full, the program will jump to location 004h and be - gins execution. location 008h this area is reserved for the timer counter 0 interrupt service program. if a timer interrupt results from a timer counter 0 overflow, and if the interrupt is enabled and the stack is not full, the program will jump to location 008h and begins execution. location 00ch this area is reserved for the timer 2 interrupt service program. if a timer interrupt resulting from a timer 2 overflow, and if the interrupt is enabled and the stack is not full, the program will jump to location 00ch and begins execution. location 010h this area is reserved for the keyscan interrupt when the keyscan function is enabled and the stack is not full, the program begins execution a location 010h on each common clock. location 014h this location is reserved for real time clock (rtc) in- terrupt service program. when the rtc generator is enabled and time-out occurs, the rtc interrupt is en- abled and the stack is not full, the program begins ex - ecution at location 014h. location 018h this area is reserved for the pwm d/a buffer empty interrupt service program. after the system latch a d/a code at ram address 28h, if the interrupt is enabled and the stack is not full, the program begins execution at location 018h. location 020h for best condition, this location is reserved at the be - ginning when writing a program. rom bank 1~3 (bp5~bp6=01b~11b) the range of the rom starts from n000h to (n+1) fffh. (n=2,4,6) table location any location in the rom space can be used as look up table. the instructions tabrdc [m] (use for any bank) and tabrdl [m] (only used for last page of program rom) transfers the contents of the lower-order byte to the specified data memory, and the higher-order byte to tblh (08h). only the desti - nation of the lower-order byte in the table is & & & & + & & & " + & & & * + 8 - / , - 6 @ / - - / - - - 7 - - & - - 7 ' $ - 7 % 4 4 4 + - ( - - 7 & & & + ! - - - 7 & & ' & + & & ' " + . - 1 - - 7 & & ' * + & & ( & + program memory HT23B60 rev. 1.10 10 march 1, 2004 well-defined, the higher-order byte of the table word are transferred to the tblh. the table higher-order byte register (tblh) is read only. the table pointer (tbhp, tblp) is a read/write register (1fh, 07h), used to indicate the table location. before accessing the table, the location must be placed in tblp. the tblh is read only and cannot be restored. if the main routine and the isr (interrupt service routine) both employ the table read instruction, the contents of the tblh in the main routine are likely to be changed by the table read instruction used in the isr. if this hap - pens, errors can occur. in other words, using the table read instruction in the main routine and the isr simul - taneously should be avoided. however, if the table read instruction has to be applied in both the main rou - tine and the isr, the interrupts should be disabled prior to the table read instruction. it should not be en - abled until the tblh has been backed up. all table re - lated instructions need two cycles to complete the operation. these areas may function as normal pro - gram memory depending upon requirements. stack register stack this is a special part of memory which is used to save the contents of the program counter (pc) only. the stack is organized into 8 levels and is neither part of the data nor program space, and is neither readable nor writeable. the activated level is indexed by the stack pointer (sp) and is neither readable nor writeable. at a subroutine call or interrupt acknowledgment, the con- tents of the program counter are pushed onto the stack. at the end of a subroutine or an interrupt routine, sig- naled by a return instruction ( ret or reti ), the pro- gram counter is restored to its previous value from the stack. after a chip reset, the sp will point to the top of the stack. if the stack is full and a non-masked interrupt takes place, the interrupt request flag will be recorded but the acknowl - edge will be inhibited. when the stack pointer is decre - mented (by ret or reti), the interrupt will be serviced. this feature prevents stack overflow allowing the pro - grammer to use the structure more easily. in a similar case, if the stack is full and a call is subse - quently executed, stack overflow occurs and the first en - try will be lost (only the most recent eight return address are stored). data memory ram the data memory is designed with (192 12) 8 bits. the data memory is divided into two functional groups: spe - cial function registers and general purpose data mem - ory. most are read/write, but some are read only. bank 0 (bp4~bp0=0000h) the bank 0 data memory includes special purpose and general purpose memory. the special purpose memory is addressed from 00h to 3fh. the special function registers include the indirect addressing reg - isters (iar0:00h, iar1:02h), timer counter 0 higher order byte register (tmr0h: 0ch), timer counter 0 lower order byte register (tmr0l: 0dh), timer counter 0 control register (tmr0c: 0eh), timer 2 lower-order byte register (tmr2l:2bh), timer 2 higher-order byte register (tmr2h:2ah), timer 2 control register (tmr2c:2ch), real timer clock control register (rtc: 24h), program counter lower-order byte register (pcl: 06h), memory pointer registers (mp0: 01h, mp1:03h), accumulator (acc:05h), table pointer lower-order byte register (tblp: 07h), table pointer higher-order byte register (tbhp:1fh), table higher-order byte register(tblh:08h), status register (status:0ah), interrupt control register 0 (intc0:0bh), interrupt control register 1 (intc1:1eh), watchdog timer option setting register (wdts:09h), pll control register (opmode:26h), lcd control register (lcdc:2dh), lcd bright control register (vlcdc:34h), lcd segment output port 0 data register (lcdpc: 37h), lcd segment output port 0 control register (lcdpcc: 38h), lcd segment output port 1 data register (lcdpd:39h), lcd seg- ment output port 1 control register (lcdpdc:3ah), pfd control register (pfdc:2fh), pwm data register (pwm:31h), pwm control register (pwmc:30h), se- rial data register (srd:33h), serial control register (src:32h), i/o registers (pa:12h, pb:14h) , i/o con - trol registers (pac:13h, pbc:15h) and pull-high con - trol register (paphc:35h, pbphc:36h). the general purpose data memory, addressed from 40h to ffh, is used for data and control information under instruction commands. all data memory areas can handle arithmetic, logic, increment, decrement and rotate operations directly. except for some dedi - cated bits, each bit in the data memory can be set and reset by the set [m].i and clr [m].i instructions, respectively. they are also indirectly accessible instruction table location *14 *13 *12 *11 *10 *9 *8 *7 *6 *5 *4 *3 *2 *1 *0 tabrdc [m] #6 #5 #4 #3 #2 #1 #0 @7 @6 @5 @4 @3 @2 @1 @0 tabrdl [m] 1111111@7@6@5@4@3@2@1@0 table location note: @7~@0: tblp register bit7~bit0 *14~*0: current program rom table address bit14~bit0 #6~#0: tbhp register bit6~bit0 HT23B60 rev. 1.10 11 march 1, 2004 through the memory pointer registers (mp0;01h, mp1;03h). bank 1~11(bp4~pb0=0001b~1011b) the range of ram starting from 40h to ffh are for general purpose. only mp1 can deal with the memory of this range. bank 15 (bp4~bp0=1111b) the range of ram starts from 80h to fbh (bch~bfh can t be used). every bit stands for one dot on the lcd. if the bit is 1 , the light of the dot on the lcd will be turned on. if the bit is 0 , then it will be turned off. only mp1 can deal with the memory of this range. the contrast form of ram location, common, and segment is as follows. lcd driver output the maximum output number of the HT23B60 lcd driver is 11 60. the common output signal can be se - lected as 11 com or 10 com and 1/4 or 1/5 bias by mask option. the lcd driver used the voltage of vlcd pin to the power source. to adjust the view angle, the pro - grammer can select the real lcd power by the register 34h. some of the segment outputs share pins with keyscan outputs (seg0~15). whether segment output or keyscan outputs can be determined by software option. lcd driver output can be enabled or disabled by setting the lcd (bit7 of lcdc; 2dh) without the influence of the related memory condition. only mp1 can deal with the memory of this range. the contrast form of ram loca- tion, common and segment is as follows: register label bits r/w function lcdc (2dh) 0~1 ro unused bit, read as 0 lven 2 rw to enable/disable the low voltage detection function (0: disable; 1: enable) 3r unused bit, read as 0 lvfg 4 ro 1: lbin pin voltage is less than low voltage detection level 0: lbin voltage is not less than low voltage detection level 5, 6 r unused bit, read as 0 lcdon 7 rw to enable/disable the lcd output (0: disable; 1: enable) lcdc register ' & & + & ' + & ( + & ) + & " + & # + & $ + & % + & * + & = + & + & 3 + & + & + & 6 + & 4 + ' & + ' ' + ' ( + ' ) + ' " + ' # + ' $ + ' % + ' * + ' = + ' + ' 3 + ' + 3 3 - 1 - - - 1 - / - 3 - 1 - - 3 - 1 - / - / - - - / - 3 - - ' 7 / - - + a - 3 - 4 ' + ' 6 + ' 4 + ( & + ( ' + ( ( + ( ) + ( " + ( # + ( $ + ( % + ( * + ( = + ( + ( 3 + ( + ( + ( 6 + ( 4 + ) & + ) ' + ) ( + ) ) + ) 4 + " & + 4 4 + " & + 4 4 + d - / - 3 0 - & - - > ' = ( - 3 ? / - 3 0 - ' - - > ' = ( - 3 ? & & ' ' 3 3 3 + . & & + & & - - - & - - & - - - ' - - ' 3 0 - / - - ; a 7 - 7 / - - ; a - 3 - 7 / - + a - 3 - . - - - - - - / - - & - - & - + a - 3 - - - & - ; a - 3 - - - & - / - 6 ( + ( ( / - - / 0 - / - - - > - / ? - - ( - + a - 3 - - - ( - ; a - 3 - - - ( - / - - 8 - / - 4 - / - . . . - / - . - - / - / - / - - < - 3 - / - - - / / a - / - - 3 - / / a - / - - - - & - - - - - & - / - - - - ' - - - - - ' - / - ) " + ) # + ) $ + ) % + ) * + ) = + ) + + 3 + ) 3 + / - 3 0 - ' ' - - > ' = ( - 3 ? " & + 4 4 + * & + 4 3 + 3 0 - ' # - - > ' ( & - 3 ? 3 + ram mapping HT23B60 rev. 1.10 12 march 1, 2004 vlcdc register (34h) lcd level bit7 bit6 bit5 bit4 10000 0.66 vlcd 20001 0.68 vlcd 30010 0.70 vlcd 40011 0.72 vlcd 50100 0.74 vlcd 60101 0.77 vlcd 70110 0.80 vlcd 80111 0.83 vlcd 91000 0.86 vlcd 101001 0.88 vlcd 111010 0.90 vlcd 121011 0.92 vlcd 131100 0.94 vlcd 141101 0.96 vlcd 151110 0.98 vlcd 161111 1.00 vlcd note: vlcd=2.4v~5.5v the range of ram starts from 80h to fbh address 80h 81h 82h 83h 84h 85h 86h ----b4h b5h b6h b8h b9h bah bbh com0 bit0 com1 bit1 com2 bit2 com3 bit3 com4 bit4 com5 bit5 com6 bit6 com7 bit7 address c0h c1h c2h c3h c4h c5h c6h - - - f5h f6h f7h f8h f9h fah fbh com8 bit0 com9 bit1 com10 bit2 seg0 seg1 seg2 seg3 seg4 seg5 seg6-seg53 seg54 seg55 seg56 seg57 seg58 seg59 lcd display memory: (bank15) note: c0~fb, bit3~7, r=0 bch~bfh, r=0; fc~ffh, r=0 1: lcd pixels on 0: lcd pixels off HT23B60 rev. 1.10 13 march 1, 2004 an example of an lcd driving waveform is shown below: 1/11 duty, 1/5 bias ' ( ) " # $ % * ' & ( " + , & < " 1 # < ) 1 # < ( 1 # < ' 1 # < ' 6 & " $ : # " + , = ' & ' ' - ' - ( - ) - " - # $ % * = ' & ' ' - ' - ( - ) < " 1 # < ) 1 # < ( 1 # < ' 1 # < < " 1 # < ) 1 # < ( 1 # < ' 1 # < 1/10 duty, 1/5 bias ' ( ) " # $ % * ' & ( " + , & < " 1 # < ) 1 # < ( 1 # < ' 1 # < ' 6 & # ' : ( + , = ' & - ' - ( - ) - " - # $ % * = ' & - ' - ( - ) < " 1 # < ) 1 # < ( 1 # < ' 1 # < < " 1 # < ) 1 # < ( 1 # < ' 1 # < HT23B60 rev. 1.10 14 march 1, 2004 1/11 duty, 1/4 bias 1/10 duty, 1/4 bias ' ( ) " # $ % * ' & ( " + , & < ) 1 " < ( 1 " < ' 1 " < ' < ) 1 " < ( 1 " < ' 1 " < 6 & < ) 1 " < ( 1 " < ' 1 " < " $ : # " + , = ' & ' ' - ' - ( - ) - " - # $ % * = ' & ' ' - ' - ( - ) ' ( ) " # $ % * ' & ( " + , & < ) 1 " < ( 1 " < ' 1 " < ' < ) 1 " < ( 1 " < ' 1 " < 6 & < ) 1 " < ( 1 " < ' 1 " < # ' : ( + , = ' & - ' - ( - ) - " - # $ % * = ' & - ' - ( - ) HT23B60 rev. 1.10 15 march 1, 2004 indirect addressing register locations 00h and 02h are indirect addressing regis - ters that are not physically implemented. any read/write operation of [00h] and [02h] access data memory pointed to by mp0 (01h) and mp1 (03h) respectively. reading location 00h or 02h indirectly returns the result 00h, while writing to it results in no operation. the data movement function between two indirect ad - dressing registers is not supported. the memory pointer registers mp0 and mp1, are 8-bit registers used to ac - cess the data memory by combining corresponding indi - rect addressing registers, bank1~bank11 and bank15 can use mp1 only. accumulator the accumulator is closely related to alu operations. it is mapped to location 05h of the data memory and can also operate with immediate data. the data movement between two data memory must pass through the accu - mulator. arithmetic and logic unit alu this circuit performs 8-bit arithmetic and logic operation. the alu provides the following functions: arithmetic operations (add, adc, sub, sbc, daa) logic operations (and, or, xor, cpl) rotation (rl, rr, rlc, rrc) increment and decrement (inc, dec) branch decision (sz, snz, siz, sdz ....) the alu not only saves the results of a data operation but can also change the status register. status register status this 8-bit register (0ah) contains the zero flag (z), carry flag (c), auxiliary carry flag (ac), overflow flag (ov), power down flag (pdf) and watchdog time-out flag (to). it also records the status information and controls the operation sequence. with the exception of the to and pdf flags, bits in the status register can be altered by instructions like any other register. any data written into the status register will not change the to or pdf flags. in addition, opera - tions related to the status register may give different re - sults from those intended. the to and pdf flags can only be changed by a system power up, watchdog timer overflow, executing the halt instruction and clearing the watchdog timer. the z, ov, ac and c flags generally reflect the status of the latest operations. in addition, on entering the interrupt sequence or exe - cuting the subroutine call, the status register will not be pushed onto the stack automatically. if the contents of the status register are important and the subroutine can corrupt the status register, the programmer must take precautions to save it properly. interrupt the HT23B60 provides external and a d/a interrupt and internal timer counter interrupts. the interrupt control register (intc;0bh, intch;1eh) contains the interrupt control bits to set the enable/disable and the interrupt re - quest flags. once an interrupt subroutine is serviced, all other inter - rupts will be blocked (by clearing the emi bit). this scheme may prevent any further interrupt nesting. other interrupt requests may occur during this interval but only the interrupt request flag is recorded. if a certain interrupt needs servicing within the service routine, the emi bit and the corresponding intc bit may be set to allow interrupt nesting. if the stack is full, the interrupt request will not be acknowledged, even if the related interrupt is enabled, un- til the sp is decremented. if immediate service is desired, the stack must be prevented from becoming full. all these kinds of interrupt have a wake-up capability. as an interrupt is serviced, a control transfer occurs by pushing the program counter and a14~a13 bits onto the register labels bits function status (0ah) c0 c is set if an operation results in a carry during an addition operation or if a borrow does not take place during a subtraction operation; otherwise c is cleared. it is also affected by a rotate through carry instruction. ac 1 ac is set if an operation results in a carry out of the low nibbles in addition or no bor - row from the high nibble into the low nibble in subtraction; otherwise ac is cleared. z2 z is set if the result of an arithmetic or logical operation is zero; otherwise z is cleared. ov 3 ov is set if an operation results in a carry into the highest-order bit but not a carry out of the highest-order bit, or vice versa; otherwise ov is cleared. pdf 4 pdf is cleared by either a system power-up or executing the clr wdt instruc - tion. pdf is set by executing the halt instruction. to 5 to is cleared by a system power-up or executing the clr wdt or halt in - struction. to is set by a wdt time-out. 6,7 unused bit, read as 0 HT23B60 rev. 1.10 16 march 1, 2004 stack and then branching to subroutines at specified lo - cations in the program memory. only the program coun - ter are pushed and a14~a13 bits onto the stack. if the contents of the register and status register (status) are altered by the interrupt service program which cor - rupt the desired control sequence, the contents must be saved first. external interrupt is triggered by a high to low transition of int which sets the related interrupt request flag (eif; bit 4 of intc0). when the interrupt is enabled, and the stack is not full and the external interrupt is active, a sub - routine call to location 04h will occur. the interrupt re - quest flag (eif) and emi bits will be cleared to disable other interrupts. the internal timer counter 0 interrupt is initialized by set - ting the timer counter 0 interrupt request flag (t0f; bit 5 of intc0), caused by a timer counter 0 overflow. when the interrupt is enabled, and the stack is not full and the t0f bit is set, a subroutine call to location 08h will occur. the related interrupt request flag (t0f) will be reset and the emi bit cleared to disable further interrupts. the timer counter 2 interrupt is operated in the same manner as timer counter 0. the related interrupt control bits et2i and t2f of timer counter 2 are bit 3 and bit 6 of intc0 respectively. the real time clock interrupt is generated by a 2hz rtc generator. when the rtc time-out occurs, the interrupt request flag rtcf will be set. when the rtc interrupt is enabled, the stack is not full and the rtcf is set, a sub- routine call to location 14h will occur. the interrupt re- quest flag rtcf and emi bits will be cleared to disable other interrupts. the keyscan interrupt is generated by lcd enable func- tion. when the bit7 of the lcdc (2dh) is set 1 , for ev - ery frame, each have a common signal all of which can generate a single interrupt. and the keyscan function have to be completed in the period of interrupt time. during the execution of an interrupt subroutine, other inter - rupt acknowledgments are held until the reti instruction is executed or the emi bit and the related interrupt control bit are set to 1 (of course, if the stack is not full). to return from the interrupt subroutine, the ret or reti instruction may be invoked. reti will set the emi bit to enable an inter - rupt service, but ret will not. interrupts occurring in the interval between the rising edges of two consecutive t2 pulses, will be serviced on the latter of the two t2 pulses, if the corresponding inter - rupts are enabled. in the case of simultaneous requests, the following table shows the priority that is applied. these can be masked by resetting the emi bit. interrupt source priority vector external interrupt 1 04h timer counter 0 overflow 2 08h timer counter 2 overflow 3 0ch keyscan interrupt 4 10h rtc interrupt 5 14h pwm d/a interrupt 6 18h emi, eei, et0i, et2i, eksi, ertci, epwmi are used to control the enabling/disabling of interrupts. these bits pre - vent the requested interrupt from being serviced. once the interrupt request flags (eif, t0f, t2f, ksf, rtcf, pwmf) are set by hardware or software, they will remain in the intc0 or intc1 r egisters until the interrupts are ser- viced or cleared by a software instruction. it is recommended that application programs do not use call subroutines within an interrupt subroutine. inter- rupts often occur in an unpredictable manner or need to be serviced immediately in some applications. if only one stack is left and the interrupt enable is not well con - trolled, once a call subroutine, if used in the interrupt subroutine, will corrupt the original control sequence. register label bit no. function intc0 (0bh) emi 0 master (global) interrupt (1=enable; 0=disable) eei 1 external interrupt (1=enable; 0=disable) et0i 2 timer counter 0 interrupt (1=enable; 0=disable) et2i 3 timer counter 2 interrupt (1=enable; 0=disable) eif 4 external interrupt request flag (1=active; 0=inactive) t0f 5 internal timer counter 0 request flag. (1=active; 0=inactive) t2f 6 internal timer counter 2 request flag. (1=active; 0=inactive) 7 unused bit, read as 0 HT23B60 rev. 1.10 17 march 1, 2004 register label bit no. function intc1 (1eh) eksi 0 controls the keyscan interrupt. (1=enable; 0=disable) ertci 1 controls the rtc interrupt. (1=enable; 0=disable) epwmi 2 pwm d/a interrupt (1=enable; 0=disable) 3 should be set 0 always. ksf 4 keyscan interrupt request flag. (1=active; 0=inactive) rtcf 5 rtc interrupt request flag. (1=active; 0=inactive) pwmf 6 pwm d/a flag (1=enable; 0=disable) 7 should be set 0 always. intch register oscillator configuration there are two oscillator circuits in the controller, the ex - ternal 32768hz crystal oscillator and internal wdt rc oscillator. the 32768hz crystal oscillator and frequency-up con - version circuit (32768hz to 3.58mhz) are designed for dual system clock source. it is necessary for the fre - quency conversion circuit to add external rc compo - nents to make up the low pass filter that stabilize the output frequency 3.58mhz (see the oscillator circuit). the wdt rc oscillator is a free running on-chip rc os- cillator, and no external components are required. even if the system enters the idle mode (the system clock is stopped), the wdt rc oscillator still works within a pe- riod of 65 s~78 s. when the wdt is disabled or the wdt source is not this rc oscillator, the wdt rc oscillator will be disabled. watchdog timer wdt the wdt clock source is implemented by a wdt osc or external 32768hz or an instruction clock (system clock divided by 4), determined by mask option. this timer is designed to prevent software malfunction or protect the sequence from jumping to an unknown loca - tion with unpredictable results. the watchdog timer can be disabled by mask option. if the watchdog timer is disabled, all the executions related to the wdt result in no operation. if the device operates in a noisy environment, using the on-chip wdt osc or 32768hz crystal oscillator is strongly recommended. when the wdt clock source is selected, it will be first di- vided by 512 (9-stage) to get the nominal time-out pe- riod. by invoking the wdt prescaler, longer time-out periods can be realized. writing data to ws2, ws1, ws0 can give different time-out periods. the wdt osc period is 78 s. this time-out period may vary with temperature, vdd and process variations. the wdt osc always works for any operation mode. if the instruction clock is selected as the wdt clock source, the wdt operates in the same manner except in the sleep mode or idle mode. in these two modes, the wdt stops counting and lose its protecting purpose. in this situation the logic can only be re-started by external logic. register label bits r/w function wdts (09h) ws0 ws1 ws2 0 1 2 rw watchdog timer division ratio selection bits bit 2, 1, 0=000, division ratio=1:1 bit 2, 1, 0=001, division ratio=1:2 bit 2, 1, 0=010, division ratio=1:4 bit 2, 1, 0=011, division ratio=1:8 bit 2, 1, 0=100, division ratio=1:16 bit 2, 1, 0=101, division ratio=1:32 bit 2, 1, 0=110, division ratio=1:64 bit 2, 1, 0=111, division ratio=1:128 7~3 rw unused bit. these bits are read/write-able. ' ( ' # 0 ) 4 # & 4 ) ( % $ * system oscillator circuit HT23B60 rev. 1.10 18 march 1, 2004 the high nibble and bit3 of the wdts are reserved for user defined flags, which can be used to indicate some specified status. the wdt time-out under normal mode or green mode will initialize chip reset and set the status bit to . but in the sleep mode or idle mode, the time-out will initial - ize a warm reset and only the program counter and stack pointer are reset to 0. to clear the wdt contents (including the wdt prescaler), three methods are adopted; external reset (a low level to res pin), soft - ware instruction and halt instruction. the software instruction include clr wdt and the other set clr wdt1 and clr wdt2 . of these two types of instruction, only one can be active depending on the mask option wdt instr .ifthe clr wdt is se- lected (i.e. one clear instruction), any execution of the clr wdt instruction will clear the wdt. in the case wherein clr wdt1 and clr wdt2 are chosen (i.e. two clear instructions), these two instructions must be executed to clear the wdt; otherwise, the wdt may reset the chip as a result of time-out. controller operation mode data bank controllers support two system clocks and four operation modes. the system clock could be 32768hz or 3.58mhz and the operation mode could be normal, green, sleep or idle mode. there are all se - lected by the software. the following conditions will force the operation mode to change to green mode: any reset condition from any operation mode any interrupt from sleep mode or idle mode a falling edge on any pin of port a from sleep mode or idle mode how to change the operation mode normal mode to green mode: step 1: clear mode1 to 0 after step 1, operation mode is changed to green mode but the pllen status has no change. however, pllen can be cleared by software. - / 0 1 " = a 7 - . - / % a 7 - * a a ' - . - a . & 5 . ( 0 / . - ) ( % $ * + , watchdog timer register label bits r/w function opmode (26h) 4~0 ro unused bit, read as 0 pllen 5 rw 1: enable the frequency up conversion function to generate 3.58mhz 0: disable the frequency up conversion function to generate 3.58mhz mode0 6 rw 0: enable the 32768hz oscillator while the halt instruction is executed 1: disable the 32768hz oscillator while the halt instruction is executed mode1 7 rw 1: select 3.58mhz as cpu system clock 0: select 32768hz as cpu system clock operation mode description halt instruction mode1 mode0 pllen operation mode 32768hz 3.58mhz system clock not execute 1 x 1 normal on on 3.58mhz not execute 0 x 0 green on off 32768hz executed 0 0 0 sleep on off halt executed 0 1 0 idle off off halt note: x means don t care HT23B60 rev. 1.10 19 march 1, 2004 normal mode or green mode to sleep mode: step 1: clear mode0 to 0 step 2: execute the halt instruction after step 2, the operation mode is changed to sleep mode, the pllen and mode1 are cleared to 0 by hardware. normal mode or green mode to idle mode: step 1: set mode0 to 1 step 2: execute the halt instruction after step 2, the operation mode is changed to idle mode, the pllen and mode1 are cleared to 0 by hardware. green mode to normal mode: step 1: set pllen to 1 step 2*: software delay 2ms at least step 3: set mode1 to 1 after step 3, operation mode is changed to normal mode. note: * must delay 20ms at least, if you want to use stable clock source sleep mode or idle mode to green mode: method 1: any reset condition occurred method 2: any interrupt is active method 3: a falling edge on any pin of port a after any source of the above descriptions, operation mode is changed to green mode. the reset conditions include power on reset, external reset, wdt time-out reset. by examining the processor status flags, pdf and to, the program can distinguish between different reset conditions . refer to the reset function for detailed description. a falling edge on port a and interrupt can be considered as a continuation of normal execution. each bit in port a can be independently selected to wake-up the device by mask option. awakening from port a stimulus, the pro - gram will resume execution of the next instruction. the interrupts from the sleep mode or idle mode may cause two sequences to occur in the controller. one is if the related interrupt is disabled or the interrupt is en - abled but the stack is full, the program will resume exe - cution at the next instruction. the other is if the interrupt is enabled and the stack is not full, the regular interrupt response takes place. it is necessary to mention that if an interrupt request flag is set to 1 before entering the sleep mode or idle mode, the wake-up function of the related interrupt will be disabled. once idle mode wake-up event occurs, it will take 1024 system clock period or sst delay time to resume to green mode. in this case, a dummy period is inserted after a wake-up. if the wake-up results from an interrupt acknowledge signal, the actual interrupt subroutine exe - cution will be delayed by one or more cycles. if the wake-up results in the next instruction execution, this will be executed immediately after the dummy period is completed. to minimize power consumption, all the i/o pins should be carefully managed before entering the sleep mode or idle mode. the sleep mode or idle mode is initialized by the halt instruction and results in the following. the system clock will be turned off the wdt function will be disabled if the wdt clock source is the instruction clock the wdt function will be disabled if the wdt clock source is the 32768hz in idle mode the wdt will still function if the wdt clock source is the wdt osc if the wdt function is still enabled, the wdt counter and wdt prescaler will be cleared and recounted again the contents of the on chip ram and registers remain unchanged all the i/o ports maintain their original status the pdf flag is set and the to flag is cleared by hard - ware. & - - ( - - - " - - - $ - - * - ' & - ' ( - ' " - ' $ - ' * - ( & > + , ? < e ) < ) : # * > ? HT23B60 rev. 1.10 20 march 1, 2004 reset there are three ways in which a reset can occur. power on reset a low pulse onto res pin time-out after these reset conditions, the program counter and stack pointer will be cleared to 0. to guarantee that the system oscillator is started and stabilized, the system start-up timer or sst provides an extra-delay of 1024 system clock pulses when the system is reset or awakes from the sleep or idle opera - tion mode. by examining the processor status flags pd and to, the software program can distinguish between the different chip resets . to pd reset condition 0 0 power on reset uu external reset during normal mode or green mode 01 external reset during sleep mode or idle mode 1u wdt time-out during normal mode or green mode 11 wdt time-out during sleep mode or idle mode note: u stands for unchanged the functional unit chip reset status are shown below: program counter 000h interrupt disabled prescaler cleared wdt cleared after a master reset, wdt begins counting (if the wdt function is en- abled by mask option) timer counter 2 off input/output port input mode stack pointer points to the top of the stack lcd display disable 6 < - a - - reset timing chart . - . / - + 2 ! ' & a 7 - / . - a 6 @ / - - - 6 reset configuration < 6 ' & & 0 & : ' 4 reset circuit HT23B60 rev. 1.10 21 march 1, 2004 when the reset conditions occurred, some registers may be changed or unchanged. register addr. reset conditions power on res pin res pin (sleep/idle) wdt wdt (sleep/idle) iar0 00h xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu mp0 01h xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu iar1 02h xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu mp1 03h xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu bp 04h 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu acc 05h xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu pcl 06h 0000h 0000h 0000h 0000h 0000h tblp 07h xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu tblh 08h xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu wdts 09h 0000 0111 0000 0111 0000 0111 0000 0111 uuuu uuuu status 0ah --00 xxxx --uu uuuu --01 uuuu --1u uuuu --11 uuuu intc0 0bh 0000 0000 0000 0000 0000 0000 0000 0000 0uuu uuuu tmr0h 0ch xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu tmr0l 0dh xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu tmr0c 0eh 0000 1000 0000 1000 0000 1000 0000 1000 uu0u u000 pa 12h 1111 1111 1111 1111 1111 1111 1111 1111 uuuu uuuu pac 13h 1111 1111 1111 1111 1111 1111 1111 1111 uuuu uuuu pb 14h 1111 1111 1111 1111 1111 1111 1111 1111 uuuu uuuu pbc 15h 1111 1111 1111 1111 1111 1111 1111 1111 uuuu uuuu intc1 1eh 0000 -000 0000 -000 0000 -000 -000 -000 0uuu 0uuu tbhp 1fh xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu rtc 24h 0000 0000 u0u0 0000 u0u0 0000 u0u0 0000 u0u0 0000 opmode 26h 0100 0000 01u0 0000 01u0 0000 01u0 0000 01u0 0000 tmr2h 2ah xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu tmr2l 2bh xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu tmr2c 2ch 0000 1000 0000 1000 0000 1000 0000 1000 uu0u u000 lcdc 2dh 0000 0000 0000 0000 0000 0000 0000 0000 u00u 0u00 pfdc 2fh 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uu00 pwmc 30h 1111 1111 1111 1111 1111 1111 1111 1111 uuuu uuuu pwm 31h xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu src 32h 0001 0000 0001 0000 0001 0000 0001 0000 uuuu uuuu srd 33h 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu vlcd 34h 0000 0000 0000 0000 0000 0000 0000 0000 uuuu 0000 paphc 35h 1111 1111 1111 1111 1111 1111 1111 1111 00uu uuuu pbphc 36h 0011 1111 0011 1111 0011 1111 0011 1111 uuuu uuuu lcdpc 37h 1111 1111 1111 1111 1111 1111 1111 1111 uuuu uuuu lcdpcc 38h 1111 1111 1111 1111 1111 1111 1111 1111 uuuu uuuu lcdpd 39h 1111 1111 1111 1111 1111 1111 1111 1111 uuuu uuuu lcdpdc 3ah 1111 1111 1111 1111 1111 1111 1111 1111 uuuu uuuu ram (data & lcd) x u u u u note: u stands for unchanged x stands for unknown - stands for unused HT23B60 rev. 1.10 22 march 1, 2004 timer 0 the timer 0 contains 16-bit programmable count-up counters and the clock source come from the system clock divided by 4. there are three registers related to the timer counter 0; tmr0h (0ch), tmr0l (0dh), tmr0c(0eh). writing tmr0l only writes the data into a low byte buffer, and writing tmr0h will simultaneously write the data and the contents of the low byte buffer into the timer 0 preload register (16-bit). the timer 0 preload register is changed by writing tmr0h operations and writing tmr0l will keep the timer 0 preload register un - changed. reading tmr0h will also latch the tmr0l into the low byte buffer to avoid any false timing problem. reading tmr0l returns the contents of the low byte buffer. in this case, the low byte of the timer counter 0 cannot be read directly. it must read the tmr0h first to make the low byte contents of the timer 0 be latched into the buffer. the tmr0c is the timer 0 control register, which de- fines the timer 0 options. the timer counter control reg- isters define the operating mode, counting enable or disable and active edge. if the timer counter starts counting, it will count from the current contents in the timer counter to ffffh. once an overflow occurs, the counter is reloaded from the timer counter preload register and at the same time generates the corresponding interrupt request flag (t0f; bit of the intc0). to enable the counting operation, the timer on bit (ton; bit 4 of the tmr0c) should be set to 1. the over - flow of the timer counter is one of the wake-up sources. no matter what the operation mode is, writing a 0 to et0i can disable the corresponding interrupt service. in the case of timer counter off condition, writing data to the timer counter preload register will also reload that data to the timer counter. but if the timer counter is turned on, data written to the timer counter will only be kept in the timer counter preload register. the timer counter will still operate until overflow occurs. when the timer counter (reading tmr0h) is read, the clock will be blocked to avoid errors. as this may result in a counting error, this must be taken into consideration by the programmer. timer 2 the timer 2 contains 16-bit programmable count-up counters whose clock may come from the 32768 hz os - cillator or the clock source come from the system clock divided by 4. there are three registers related to the timer counter 2; tmr2h (2ah), tmr2l (2bh), tmr2c(2ch). writing tmr2l only writes the data into a low byte buffer, and writing tmr2h will simultaneously write the data and the contents of the low byte buffer into the timer 2 preload register (16-bit). the timer 2 preload register is changed by writing tmr2h operations and writing - - & / - - - & - 3 / 8 / ; - ; - 3 - 3 2 - ! 1 " register label bits r/w function tmr0c (0eh) 0~2 ro unused bit, read as 0 3 unused bit, read as 0 ton 4 rw enable/disable the timer counting (0=disabled; 1=enabled) 5 unused bit, read as 0 tm0 tm1 6 7 rw fixed bit 7, 6=10, internal timer mode register label bits r/w function tmr2c (2ah) 0~3 unused bit, read as 0 ton 4 rw enable/disable the timer counting (0=disabled; 1=enabled) 5 unused bit, read as 0 tm0 tm1 6 7 rw fixed bit 7, 6=10, internal timer mode HT23B60 rev. 1.10 23 march 1, 2004 tmr2l will keep the timer 2 preload register un - changed. reading tmr2h will also latch the tmr2l into the low byte buffer to avoid any false timing problem. reading tmr2l returns the contents of the low byte buffer. in other words, the low byte of the timer counter 2 cannot be read directly. it must read the tmr2h first to make the low byte contents of timer 2 be latched into the buffer. the tmr2c is the timer 2 control register, which de - fines the timer 2 options. the timer counter control reg - isters define the operating mode, counting enable or disable and active edge. if the timer counter starts counting, it will count from the current contents in the timer counter to ffffh. once an overflow occurs, the counter is reloaded from the timer counter preload register and generates the correspond - ing interrupt request flag (t2f; bit of intc0) at the same time. to enable the counting operation, the timer on bit (ton; bit 4 of tmr2c) should be set to 1. the overflow of the timer counter is one of the wake-up sources. no matter what the operation mode is, writin ga0to et0i can disable the corresponding interrupt service. in the case of timer counter off condition, writing data to the timer counter preload register will also reload that data to the timer counter. but if the timer counter is turned on, data written to the timer counter will only be kept in the timer counter preload register. the timer counter will still operate until overflow occurs. when the timer counter (reading tmr1h) is read, the clock will be blocked to avoid errors. as this may result in a counting error, this must be taken into consideration by the programmer. the timer 2 can also be used as pfd output by setting pwm1 and pwm2 to be pfd and pfdb output respec - tively by 2fh.7 and 2fh.6. when the pfd/pfdb func - tion is selected, setting 2fh.4/2fh.5 to 1 will enable the pfd/pfdb output and setting 2fh.4/2fh.5 to 0 will disable the pfd/pfdb output. - ( / - - - ( - 3 / 8 / ; - ; - 3 - 3 ) : # * + , 1 " ( ( 4 + : # ( 4 + : " ( 4 + : % . ( - . ' - ( 4 + : $ . ( . ' 4 : ) ) ( % $ * + , register label bits r/w function pfdc (2fh) 2~0 r unused bit, read as 0 tim2 3 rw 1: the timer 2 frequency source is 3.58mhz/4 0: the timer 2 frequency source is 32768hz pfdb 4 rw 1: enable pfdb 0: disable pfdb pfd 5 rw 1: enable pfd 0: disable pfd pfdb/pwm1 6 rw 1: enable pfdb 0: enable pwm1 pfd/pwm2 7 rw 1: enable pfd 0: enable pwm2 pfdc HT23B60 rev. 1.10 24 march 1, 2004 register label bits r/w function rtc (24h) 6,4 ~0 ro unused bit, read as 0 rtcen 5 rw enable/disable the rtc counting (0: disable; 1: enable) rtcset 7 rw rtc time-out flag (1: active; 0: inactive) rtc & wdt & lcd clock rtc function the real time clock (rtc) is used to supply a regular in - ternal interrupt. its time-out period is 2hz. if the rtc time-out occurs, the interrupt request flag rtcf and the rtcset flag will be set to 1. the interrupt vector for the rtc is 14h. when the interrupt subroutine is serviced, the interrupt request flag (rtcf) will be cleared to 0, but the flag rtcset maintain its original value. if rtc is time-out, the flag rtcset and rtcf will be set to 1. the flag rtcset can be cleared to 0 by software. input/output ports there are 14 bidirectional input/output lines in the HT23B60, labeled pa and pb, which are mapped to the data memory of [12h], [14h], respectively. all these i/o ports can be used for input and output operations. for input operation, these ports are non-latching, that is, the inputs must be ready at the t2 rising edge of instruction mov a,[m] (m=12h, 14h). for output operation, all data is latched and remains unchanged until the output latch is rewritten. each i/o line has its own control register (pac, pbc) to control the input/output configuration. with this control register, cmos output or schmitt trig - ger input with or without pull-high resistor (software op - tion 35h, 36h) structures can be reconfigured dynamically under software control. to function as an input, the corresponding latch of the control register must be written a 1 . the pull-high resistance will ex - hibit automatically if the pull-high option is selected. the input source also depends on the control register. if the control register bit is 1 , the input will read the pad state. if the control register bit is 0 , the contents of the latches will move to the internal bus. the latter is possi - ble in read-modify-write instruction. for output func - tion, cmos is the only configuration. these control registers are mapped to locations 13h, 15h. after a chip reset, these input/output lines remain at high levels or floating (mask option). each bit of these input/output latches can be set or cleared by the set [m].i or clr [m].i (m=12h, 14h) instruction. some instructions first input data and then follow the output operations. for ex - ample, the set [m].i , clr [m].i , cpl [m] and cpla [m] instructions read the entire port states into the cpu, execute the defined operations (bit-operation), and then write the results back to the latches or the accumulator. each line of port a has the capability to wake-up the device. port b are share pad, each pin function are defined by mask option, when the pb3 be used as a normal i/o port, int function must be disable. (set [0bh].4 to 0 ). the pb2, pb1 and pb0 share with serial data input, serial data output and serial clock. if the serial function is selected, the related i/o register (pb) cannot be used as general purpose regis - ter. reading the register will result to an unknown state. ) ( 0 + , - f 4 ' ' 1 ' $ ) * " ' 1 ' $ - 8 > ( & " * + , ? g ! g g ! g - 3 . - / - - - / - . - 1 - 1 - . 0 a - > - / ? . 0 / / a & 5 % 3 & 5 3 # < < / / a + - / - 0 - HT23B60 rev. 1.10 25 march 1, 2004 pwm interface the HT23B60 provides an 8 bit (bit 7 is a sign bit) pwm d/a interface, which is good for speech synthesis. the user can record or synthesize the sound and digitize it into the program rom. this sound could be played back in sequence of the functions as designed by the internal program rom. there are several algorithms that can be used in the HT23B60, namely, pcm, _law, dpcm, adpcm...etc. the pwm circuit consists of seven counters. when ini - tialized, qb goes high and when an overflow occurs, qb goes low. when the pwm controller bits 0 of the 30h are set as 0 , each of the 128 clock will initialize the counter and load the value that come from pwm data buffer to counter. the pwm modulation can be controlled by us- ing a different value of the pwm data buffer. a single bit can control the signal changes from the pwm1 or pwm2 output. the pwm clock source comes from the system clock divided by a 3-bit prescaler. setting data to p0, p1 and p2 (bit3, 4, 5 of 30h) can yield various clock sources. setting pwm controller bits d0, d1 (bit6, 7 of 30h) can control the interrupt as to how many times the counter overflows. bz/sp 6/7 bit f1 f2 (sampling rate) device 0 0 f0 f0/64 32 speakers 0 1 f0 f0/128 32 speakers 1 0 f0 f0/64 buzzer/ 8 speakers 1 1 f0 f0/128 buzzer/ 8 speakers note: f1: for pwm modulation clock and f2 for sam - pling clock f0: system/[n+1], n=0~7 (n: 3 bits preload counter) x stands for don t care on the sampling rate table, we can easily see that the sampling rate is dependent on the system clock. if start bit of the 30h.0 is set as 1 , the pwm2 and pwm1 will output a gnd level voltage. label bits function pwm dis/en 0 enable/disable pwm output 0: enable; 1: disable bz/sp 1 output driver select 1: buzzer; 0: speaker 6/7 bits 2 pwm counter bit select 1: 7 bits; 0: 6 bits p0~p2 3~5 3 bits preload counter bit5~3: 000b~111b (0~7); bit3: lsb d0, d1 6, 7 pwmi d1 d0 pwm interrupt 001 012 104 118 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 7-bit d7 d6 d5 d4 d3 d2 d1 d0 6-bit d7 d6 d5 d4 d3 d2 d1 x note: x stands for don t care bit7: sign bit bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 1: pull-high 1: pull-high 1: pull-high 1: pull-high 1: pull-high 1: pull-high 1: pull-high 1: pull-high 0: no pull 0: no pull 0: no pull 0: no pull 0: no pull 0: no pull 0: no pull 0: no pull pa pull-high resistor bit7~bit6 bit5 bit4 bit3 bit2 bit1 bit0 unused bit 1: pull-high 1: pull-high 1: pull-high 1: pull-high 1: pull-high 1: pull-high 0: no pull 0: no pull 0: no pull 0: no pull 0: no pull 0: no pull pb pull-high resistor HT23B60 rev. 1.10 26 march 1, 2004 4 & - 3 4 ' 4 ( - / - ' ( * - / 0 pwm - / 0 / . - 3 - > ) ' + ? % - 3 - - 3 8 / ; . ' - - ) ( - ! 4 & - 3 ) & + : & 8 : . 4 ( ! 6 4 ' < ! g g . ( - - ) ( - ! 30h.1=0 speaker - / 0 / . - 3 - > ) ' + ? % - 3 - 8 / ; 4 & - 3 8 : . 4 ( ! 6 ! g 4 ' < - 3 g . ' - - 3 h . ( - - 3 h - 7 30h.1=1 buzzer HT23B60 rev. 1.10 27 march 1, 2004 serial interface protocol (spi) 3 wire spi format, support 32kbytes/64kbytes /128k.bytes/256kbytes rising edge latch data, falling edge output data serial ram control register register label bits function src (32h) 0 unused bit, read as 0 busy 1 0: the data register is full (readable) or empty (writeable) (default=0) 1: serial ram interface is busy, cannot write/read the data register 2 unused bit, read as 0 sread 3 1: series read; 0: step read w/r 4 w/r=0: read mode; to read data from the external serial ram w/r=1: write mode; to write data to the external serial ram smode 5 spi mode setting 0: mode 0; 1: mode 3 sclk0 6 serial ram interface clock, default=0 sclk1 7 serial ram interface clock, default=0 sclk1 sclk0 serial ram interface clock selector 0 0 serial ram interface clock=system clock/2 0 1 serial ram interface clock=system clock/4 1 1 serial ram interface clock=system clock/8 1 1 serial ram interface clock=system clock/16 data are read from or written to the data register which is transmitted through the serial ram interface after the next 8-bit data are written to, it is transmitted to the 8 serial ram interface clock within the 8 serial ram interface clock, while transmission occurs the busy flag goes 1, after which, when the trans- mission is completed, the busy flag goes 0 serial ram data register address register 76543210r/w default 33h srd d7 d6 d5 d4 d3 d2 d1 d0 r/w 00000000 (1sb) spi interface information spi interface connection note: controller (master): do/di/sck is spi interface pin, pxn~pxm are generic i/o port. memory (slave): si/so/sck is spi interface pin, cs is chip select. ! ! ! HT23B60 rev. 1.10 28 march 1, 2004 spi register description the spi is used two register, one is data register, the other one is control register. and for the data register is used for data transfer/receiver register, the control register is used to control and display the status of the spi. control register bit bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sck setting sck setting spi mode setting read/writ e mode setting spi series read reserved spi busy reserved b7,b6=0,0 sck=f sys /2 b7,b6=0,1 sck=f sys /4 b7,b6=1,0 sck=f sys /8 b7,b6=1,1 sck=f sys /1 6 b5=1 mode3 b5=0 mode0 b4=1 write b4=0 read b3=1 series read b3=0 step read ro= 0 b1=1 busy, data serial out. b1=0 ready, can access data. ro= 0 note: the spi mode0 & mode3 is changed by software option. write data into memory (write mode) timing chart (mode 0) symbol parameter min. typ. max. unit t css cs setup time 0 ns t su data in setup time 1 2sck t ho data in hold time 1 2sck the following will show how to write data to memory by the way of the flowchart note: after to write the data register, the serial out is executed automatically, and the busy bit of the spi will be set to 1 , when the serial out is completed, the busy bit of the spi will be set to 0 , and can be readable/writeable in this moment. ! + a h & ' ( ) " # $ % 3 % 3 $ 3 # 3 " 3 ) 3 ( 3 ' 3 & 3 % 3 $ 3 # 3 " 3 ) 3 ( 3 ' 3 & & ' ( ) " # $ % + / > @ @ @ ' @ @ @ @ ? > - / ? > ? > ? > ? > - / ? 6 0 3 i 0 3 i 0 3 i HT23B60 rev. 1.10 29 march 1, 2004 read data from memory (read mode) timing chart (mode 0) symbol parameter min. typ. max. unit t css cs setup time 0 ns t su data in setup time 1 2sck t ho data in hold time 1 2sck the following will show how to read data from memory by the way of the flowchart ! + a h & ' ( ) " # $ % 3 % 3 $ 3 # 3 " 3 ) 3 ( 3 ' 3 & 3 % 3 $ 3 # 3 " 3 ) 3 ( 3 ' 3 & & ' ( ) " # $ % + / > @ @ @ ' @ @ @ @ ? > - / ? > ? > ? / > @ @ @ & @ @ @ @ ? ! - 8 > - / ? 6 0 3 i 0 3 i 0 3 i low voltage detected the controller provides a circuit that detects the vlcd pin voltage level. to enable this detection function, the lven should be written as 1. once this function is enabled, the detection circuit needs 100 s to be stable. after that, user could read the result from the lvfg. the low voltage detect function will consume power. for power saving, write 0 to lven if the low voltage detection function is unnecessary. the tolerance value for the 3 conditions (min, typ. max) are within 5%. HT23B60 rev. 1.10 30 march 1, 2004 keyscan lcd out port structure for every frame, each have a common signal, all of which can generate a single interrupt. the scan key performs the following: the keyscan loop with 32khz system frequency the keyscan loop executes every 2 keyscan int,. after an interrupt occurs, clear lcd segment output port turn on the pa port s pull-hi resistance turn on the lcd segment output port. use the lcd segment output port and input port pa to implement the key scan take the scan value and store into the memory turn off the lcd segment output port transition to lcd segment output. turn off the pa pull-hi return to the main routine and change system frequency the keyscan function have to be completed in the period of interrupt time. the keyscan function is generated by common signal. when the lcd function is enable, the keyscan function can be used. ' ( ) " # $ % * ' & ( " + , & < ) 1 " - < ( 1 " - < ' 1 " - < 6 & < ) 1 " - < ( 1 " - < ' 1 " - < " $ : # " + , ' ( ) " = ' & ' ' ' ' - 4 j - = ) + , 9 / - - - - k - - - - / / a + - - - - - - - - - - - - - / / a + - - - - / / a + - - - - - - - - - - - - - / / a + - - : l ( # & l ( # & g ! g ! g - 3 m - / - - g & ' 6 & 5 6 ' # - 6 & 5 ' # - 3 . - 1 - HT23B60 rev. 1.10 31 march 1, 2004 example: ;*keyscan loop executes every 2 keyscan int. clr lcdpc ;clear lcd output (seg0~seg7) clr lcdpd ;clear lcd output (seg8~seg15) set paphc ;enable pa pull-hi clr lcdpcc ;seg0~seg7 output port mov a,pa ;write pa to acc set lcdpcc ;turn on seg0~seg7 clr paphc ;disable pa pull-hi cpla acc ;complement acc sz acc ;check if stroke down jmp speed_up ;then change from normal mode to green mode set paphc ;enable pa pull-hi clr lcdpdc ;seg8~seg15 output port mov a,pa ;write pa to acc set lcdpdc ;turn on seg8~seg15 clr paphc ;disable pa pull-hi cpla acc ;complement acc sz acc ;check if stroke down jmp speed_up ;then change from normal mode to green mode reti lcd output control (38h) bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 1: seg7 1: seg6 1: seg5 1: seg4 1: seg3 1: seg2 1: seg1 1: seg0 0: output 0: output 0: output 0: output 0: output 0: output 0: output 0: output lcd output (37h) bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 (seg0) d7 d6 d5 d4 d3 d2 d1 d0 lcd output control (3ah) bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 1: seg15 1: seg14 1: seg13 1: seg12 1: seg11 1: seg10 1: seg9 1: seg8 0: output 0: output 0: output 0: output 0: output 0: output 0: output 0: output lcd output (39h) bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 (seg8) d7 d2 d5 d4 d3 d2 d1 d7 HT23B60 rev. 1.10 32 march 1, 2004 mask option the following table shows many kinds of mask option in the databank controller. all these options should be defined in order to ensure prober system functions name mask option wdt wdt source selection rc select the wdt osc to be the wdt source t1 select the instruction clock to be the wdt source 32khz select the external 32768hz to be the wdt source disable disable the wdt function wdtinstr this option defines how to clear the wdt by instruction one clear instruction the clr wdt can clear the wdt two clear instructions only when both of the clr wdt1 and clr wdt2 have been executed, then the wdt can be cleared halt option halt function selection defines the halt function either disabled or enabled wake-up pa port a wake-up selection. defines the wake-up function activity all port a have the capability to wake-up the chip from halt this wake-up function is selected per bit lcd bias register selection this option describes the lcd bias current. there are three types of selection *_selectable as small, middle or large current small current: 660k middle current: 330k large current: 66k pb0~2 share pad option defines the pad pb0~pb2 whether normal i/o pad or serial ram interface pad lcd duty option defines the lcd duty whether 1/10 or 1/11 duty lcd bias option defines the lcd bias whether 1/4 or 1/5 bias pb3 share pad option defines the pad pb3 whether int interrupt input pad or normal i/o pad application circuits HT23B60 rev. 1.10 33 march 1, 2004 & ' & 6 & 6 # = ) ( % $ * + , . ' . ( - / $ & - ' ' - 1 - - - - 1 - - ! 1 3 ) - - 3 ( - - 3 ' - - 3 & & ' ( ) " # $ % 3 # 3 " ' ( ) " # & & ' ( ' ) ' " ' # ' # 0 ) 4 # & 4 < < 3 < ' ( instruction set summary mnemonic description instruction cycle flag affected arithmetic add a,[m] addm a,[m] add a,x adc a,[m] adcm a,[m] sub a,x sub a,[m] subm a,[m] sbc a,[m] sbcm a,[m] daa [m] add data memory to acc add acc to data memory add immediate data to acc add data memory to acc with carry add acc to data memory with carry subtract immediate data from acc subtract data memory from acc subtract data memory from acc with result in data memory subtract data memory from acc with carry subtract data memory from acc with carry and result in data memory decimal adjust acc for addition with result in data memory 1 1 (1) 1 1 1 (1) 1 1 1 (1) 1 1 (1) 1 (1) z,c,ac,ov z,c,ac,ov z,c,ac,ov z,c,ac,ov z,c,ac,ov z,c,ac,ov z,c,ac,ov z,c,ac,ov z,c,ac,ov z,c,ac,ov c logic operation and a,[m] or a,[m] xor a,[m] andm a,[m] orm a,[m] xorm a,[m] and a,x or a,x xor a,x cpl [m] cpla [m] and data memory to acc or data memory to acc exclusive-or data memory to acc and acc to data memory or acc to data memory exclusive-or acc to data memory and immediate data to acc or immediate data to acc exclusive-or immediate data to acc complement data memory complement data memory with result in acc 1 1 1 1 (1) 1 (1) 1 (1) 1 1 1 1 (1) 1 z z z z z z z z z z z increment & decrement inca [m] inc [m] deca [m] dec [m] increment data memory with result in acc increment data memory decrement data memory with result in acc decrement data memory 1 1 (1) 1 1 (1) z z z z rotate rra [m] rr [m] rrca [m] rrc [m] rla [m] rl [m] rlca [m] rlc [m] rotate data memory right with result in acc rotate data memory right rotate data memory right through carry with result in acc rotate data memory right through carry rotate data memory left with result in acc rotate data memory left rotate data memory left through carry with result in acc rotate data memory left through carry 1 1 (1) 1 1 (1) 1 1 (1) 1 1 (1) none none c c none none c c data move mov a,[m] mov [m],a mov a,x move data memory to acc move acc to data memory move immediate data to acc 1 1 (1) 1 none none none bit operation clr [m].i set [m].i clear bit of data memory set bit of data memory 1 (1) 1 (1) none none HT23B60 rev. 1.10 34 march 1, 2004 mnemonic description instruction cycle flag affected branch jmp addr sz [m] sza [m] sz [m].i snz [m].i siz [m] sdz [m] siza [m] sdza [m] call addr ret ret a,x reti jump unconditionally skip if data memory is zero skip if data memory is zero with data movement to acc skip if bit i of data memory is zero skip if bit i of data memory is not zero skip if increment data memory is zero skip if decrement data memory is zero skip if increment data memory is zero with result in acc skip if decrement data memory is zero with result in acc subroutine call return from subroutine return from subroutine and load immediate data to acc return from interrupt 2 1 (2) 1 (2) 1 (2) 1 (2) 1 (3) 1 (3) 1 (2) 1 (2) 2 2 2 2 none none none none none none none none none none none none none table read tabrdc [m] tabrdl [m] read rom code (current page) to data memory and tblh read rom code (last page) to data memory and tblh 2 (1) 2 (1) none none miscellaneous nop clr [m] set [m] clr wdt clr wdt1 clr wdt2 swap [m] swapa [m] halt no operation clear data memory set data memory clear watchdog timer pre-clear watchdog timer pre-clear watchdog timer swap nibbles of data memory swap nibbles of data memory with result in acc enter power down mode 1 1 (1) 1 (1) 1 1 1 1 (1) 1 1 none none none to,pdf to (4) ,pdf (4) to (4) ,pdf (4) none none to,pdf note: x: immediate data m: data memory address a: accumulator i: 0~7 number of bits addr: program memory address : flag is affected : flag is not affected (1) : if a loading to the pcl register occurs, the execution cycle of instructions will be delayed for one more cycle (four system clocks). (2) : if a skipping to the next instruction occurs, the execution cycle of instructions will be delayed for one more cycle (four system clocks). otherwise the original instruction cycle is unchanged. (3) : (1) and (2) (4) : the flags may be affected by the execution status. if the watchdog timer is cleared by executing the clr wdt1 or clr wdt2 instruction, the to and pdf are cleared. otherwise the to and pdf flags remain unchanged. HT23B60 rev. 1.10 35 march 1, 2004 instruction definition adc a,[m] add data memory and carry to the accumulator description the contents of the specified data memory, accumulator and the carry flag are added si - multaneously, leaving the result in the accumulator. operation acc acc+[m]+c affected flag(s) to pdf ov z ac c adcm a,[m] add the accumulator and carry to data memory description the contents of the specified data memory, accumulator and the carry flag are added si - multaneously, leaving the result in the specified data memory. operation [m] acc+[m]+c affected flag(s) to pdf ov z ac c add a,[m] add data memory to the accumulator description the contents of the specified data memory and the accumulator are added. the result is stored in the accumulator. operation acc acc+[m] affected flag(s) to pdf ov z ac c add a,x add immediate data to the accumulator description the contents of the accumulator and the specified data are added, leaving the result in the accumulator. operation acc acc+x affected flag(s) to pdf ov z ac c addm a,[m] add the accumulator to the data memory description the contents of the specified data memory and the accumulator are added. the result is stored in the data memory. operation [m] acc+[m] affected flag(s) to pdf ov z ac c HT23B60 rev. 1.10 36 march 1, 2004 and a,[m] logical and accumulator with data memory description data in the accumulator and the specified data memory perform a bitwise logical_and op - eration. the result is stored in the accumulator. operation acc acc and [m] affected flag(s) to pdf ov z ac c and a,x logical and immediate data to the accumulator description data in the accumulator and the specified data perform a bitwise logical_and operation. the result is stored in the accumulator. operation acc acc and x affected flag(s) to pdf ov z ac c andm a,[m] logical and data memory with the accumulator description data in the specified data memory and the accumulator perform a bitwise logical_and op - eration. the result is stored in the data memory. operation [m] acc and [m] affected flag(s) to pdf ov z ac c call addr subroutine call description the instruction unconditionally calls a subroutine located at the indicated address. the program counter increments once to obtain the address of the next instruction, and pushes this onto the stack. the indicated address is then loaded. program execution continues with the instruction at this address. operation stack pc+1 pc addr affected flag(s) to pdf ov z ac c clr [m] clear data memory description the contents of the specified data memory are cleared to 0. operation [m] 00h affected flag(s) to pdf ov z ac c HT23B60 rev. 1.10 37 march 1, 2004 clr [m].i clear bit of data memory description the bit i of the specified data memory is cleared to 0. operation [m].i 0 affected flag(s) to pdf ov z ac c clr wdt clear watchdog timer description the wdt is cleared (clears the wdt). the power down bit (pdf) and time-out bit (to) are cleared. operation wdt 00h pdf and to 0 affected flag(s) to pdf ov z ac c 00 clr wdt1 preclear watchdog timer description together with clr wdt2, clears the wdt. pdf and to are also cleared. only execution of this instruction without the other preclear instruction just sets the indicated flag which im - plies this instruction has been executed and the to and pdf flags remain unchanged. operation wdt 00h* pdf and to 0* affected flag(s) to pdf ov z ac c 0* 0* clr wdt2 preclear watchdog timer description together with clr wdt1, clears the wdt. pdf and to are also cleared. only execution of this instruction without the other preclear instruction, sets the indicated flag which im- plies this instruction has been executed and the to and pdf flags remain unchanged. operation wdt 00h* pdf and to 0* affected flag(s) to pdf ov z ac c 0* 0* cpl [m] complement data memory description each bit of the specified data memory is logically complemented (1 s complement). bits which previously containe d a 1 are changed to 0 and vice-versa. operation [m] [m ] affected flag(s) to pdf ov z ac c HT23B60 rev. 1.10 38 march 1, 2004 cpla [m] complement data memory and place result in the accumulator description each bit of the specified data memory is logically complemented (1 s complement). bits which previously contained a 1 are changed to 0 and vice-versa. the complemented result is stored in the accumulator and the contents of the data memory remain unchanged. operation acc [m ] affected flag(s) to pdf ov z ac c daa [m] decimal-adjust accumulator for addition description the accumulator value is adjusted to the bcd (binary coded decimal) code. the accumu - lator is divided into two nibbles. each nibble is adjusted to the bcd code and an internal carry (ac1) will be done if the low nibble of the accumulator is greater than 9. the bcd ad - justment is done by adding 6 to the original value if the original value is greater than 9 or a carry (ac or c) is set; otherwise the original value remains unchanged. the result is stored in the data memory and only the carry flag (c) may be affected. operation if acc.3~acc.0 >9 or ac=1 then [m].3~[m].0 (acc.3~acc.0)+6, ac1=ac else [m].3~[m].0 (acc.3~acc.0), ac1=0 and if acc.7~acc.4+ac1 >9 or c=1 then [m].7~[m].4 acc.7~acc.4+6+ac1,c=1 else [m].7~[m].4 acc.7~acc.4+ac1,c=c affected flag(s) to pdf ov z ac c dec [m] decrement data memory description data in the specified data memory is decremented by 1. operation [m] [m] 1 affected flag(s) to pdf ov z ac c deca [m] decrement data memory and place result in the accumulator description data in the specified data memory is decremented by 1, leaving the result in the accumula - tor. the contents of the data memory remain unchanged. operation acc [m] 1 affected flag(s) to pdf ov z ac c HT23B60 rev. 1.10 39 march 1, 2004 halt enter power down mode description this instruction stops program execution and turns off the system clock. the contents of the ram and registers are retained. the wdt and prescaler are cleared. the power down bit (pdf) is set and the wdt time-out bit (to) is cleared. operation pc pc+1 pdf 1 to 0 affected flag(s) to pdf ov z ac c 01 inc [m] increment data memory description data in the specified data memory is incremented by 1 operation [m] [m]+1 affected flag(s) to pdf ov z ac c inca [m] increment data memory and place result in the accumulator description data in the specified data memory is incremented by 1, leaving the result in the accumula - tor. the contents of the data memory remain unchanged. operation acc [m]+1 affected flag(s) to pdf ov z ac c jmp addr directly jump description the program counter are replaced with the directly-specified address unconditionally, and control is passed to this destination. operation pc addr affected flag(s) to pdf ov z ac c mov a,[m] move data memory to the accumulator description the contents of the specified data memory are copied to the accumulator. operation acc [m] affected flag(s) to pdf ov z ac c HT23B60 rev. 1.10 40 march 1, 2004 mov a,x move immediate data to the accumulator description the 8-bit data specified by the code is loaded into the accumulator. operation acc x affected flag(s) to pdf ov z ac c mov [m],a move the accumulator to data memory description the contents of the accumulator are copied to the specified data memory (one of the data memories). operation [m] acc affected flag(s) to pdf ov z ac c nop no operation description no operation is performed. execution continues with the next instruction. operation pc pc+1 affected flag(s) to pdf ov z ac c or a,[m] logical or accumulator with data memory description data in the accumulator and the specified data memory (one of the data memories) per- form a bitwise logical_or operation. the result is stored in the accumulator. operation acc acc or [m] affected flag(s) to pdf ov z ac c or a,x logical or immediate data to the accumulator description data in the accumulator and the specified data perform a bitwise logical_or operation. the result is stored in the accumulator. operation acc acc or x affected flag(s) to pdf ov z ac c orm a,[m] logical or data memory with the accumulator description data in the data memory (one of the data memories) and the accumulator perform a bitwise logical_or operation. the result is stored in the data memory. operation [m] acc or [m] affected flag(s) to pdf ov z ac c HT23B60 rev. 1.10 41 march 1, 2004 ret return from subroutine description the program counter is restored from the stack. this is a 2-cycle instruction. operation pc stack affected flag(s) to pdf ov z ac c ret a,x return and place immediate data in the accumulator description the program counter is restored from the stack and the accumulator loaded with the speci - fied 8-bit immediate data. operation pc stack acc x affected flag(s) to pdf ov z ac c reti return from interrupt description the program counter is restored from the stack, and interrupts are enabled by setting the emi bit. emi is the enable master (global) interrupt bit. operation pc stack emi 1 affected flag(s) to pdf ov z ac c rl [m] rotate data memory left description the contents of the specified data memory are rotated 1 bit left with bit 7 rotated into bit 0. operation [m].(i+1) [m].i; [m].i:bit i of the data memory (i=0~6) [m].0 [m].7 affected flag(s) to pdf ov z ac c rla [m] rotate data memory left and place result in the accumulator description data in the specified data memory is rotated 1 bit left with bit 7 rotated into bit 0, leaving the rotated result in the accumulator. the contents of the data memory remain unchanged. operation acc.(i+1) [m].i; [m].i:bit i of the data memory (i=0~6) acc.0 [m].7 affected flag(s) to pdf ov z ac c HT23B60 rev. 1.10 42 march 1, 2004 rlc [m] rotate data memory left through carry description the contents of the specified data memory and the carry flag are rotated 1 bit left. bit 7 re - places the carry bit; the original carry flag is rotated into the bit 0 position. operation [m].(i+1) [m].i; [m].i:bit i of the data memory (i=0~6) [m].0 c c [m].7 affected flag(s) to pdf ov z ac c rlca [m] rotate left through carry and place result in the accumulator description data in the specified data memory and the carry flag are rotated 1 bit left. bit 7 replaces the carry bit and the original carry flag is rotated into bit 0 position. the rotated result is stored in the accumulator but the contents of the data memory remain unchanged. operation acc.(i+1) [m].i; [m].i:bit i of the data memory (i=0~6) acc.0 c c [m].7 affected flag(s) to pdf ov z ac c rr [m] rotate data memory right description the contents of the specified data memory are rotated 1 bit right with bit 0 rotated to bit 7. operation [m].i [m].(i+1); [m].i:bit i of the data memory (i=0~6) [m].7 [m].0 affected flag(s) to pdf ov z ac c rra [m] rotate right and place result in the accumulator description data in the specified data memory is rotated 1 bit right with bit 0 rotated into bit 7, leaving the rotated result in the accumulator. the contents of the data memory remain unchanged. operation acc.(i) [m].(i+1); [m].i:bit i of the data memory (i=0~6) acc.7 [m].0 affected flag(s) to pdf ov z ac c rrc [m] rotate data memory right through carry description the contents of the specified data memory and the carry flag are together rotated 1 bit right. bit 0 replaces the carry bit; the original carry flag is rotated into the bit 7 position. operation [m].i [m].(i+1); [m].i:bit i of the data memory (i=0~6) [m].7 c c [m].0 affected flag(s) to pdf ov z ac c HT23B60 rev. 1.10 43 march 1, 2004 rrca [m] rotate right through carry and place result in the accumulator description data of the specified data memory and the carry flag are rotated 1 bit right. bit 0 replaces the carry bit and the original carry flag is rotated into the bit 7 position. the rotated result is stored in the accumulator. the contents of the data memory remain unchanged. operation acc.i [m].(i+1); [m].i:bit i of the data memory (i=0~6) acc.7 c c [m].0 affected flag(s) to pdf ov z ac c sbc a,[m] subtract data memory and carry from the accumulator description the contents of the specified data memory and the complement of the carry flag are sub - tracted from the accumulator, leaving the result in the accumulator. operation acc acc+[m ]+c affected flag(s) to pdf ov z ac c sbcm a,[m] subtract data memory and carry from the accumulator description the contents of the specified data memory and the complement of the carry flag are sub - tracted from the accumulator, leaving the result in the data memory. operation [m] acc+[m ]+c affected flag(s) to pdf ov z ac c sdz [m] skip if decrement data memory is 0 description the contents of the specified data memory are decremented by 1. if the result is 0, the next instruction is skipped. if the result is 0, the following instruction, fetched during the current instruction execution, is discarded and a dummy cycle is replaced to get the proper instruc - tion (2 cycles). otherwise proceed with the next instruction (1 cycle). operation skip if ([m] 1)=0, [m] ([m] 1) affected flag(s) to pdf ov z ac c sdza [m] decrement data memory and place result in acc, skip if 0 description the contents of the specified data memory are decremented by 1. if the result is 0, the next instruction is skipped. the result is stored in the accumulator but the data memory remains unchanged. if the result is 0, the following instruction, fetched during the current instruction execution, is discarded and a dummy cycle is replaced to get the proper instruction (2 cy - cles). otherwise proceed with the next instruction (1 cycle). operation skip if ([m] 1)=0, acc ([m] 1) affected flag(s) to pdf ov z ac c HT23B60 rev. 1.10 44 march 1, 2004 set [m] set data memory description each bit of the specified data memory is set to 1. operation [m] ffh affected flag(s) to pdf ov z ac c set [m]. i set bit of data memory description bit i of the specified data memory is set to 1. operation [m].i 1 affected flag(s) to pdf ov z ac c siz [m] skip if increment data memory is 0 description the contents of the specified data memory are incremented by 1. if the result is 0, the fol - lowing instruction, fetched during the current instruction execution, is discarded and a dummy cycle is replaced to get the proper instruction (2 cycles). otherwise proceed with the next instruction (1 cycle). operation skip if ([m]+1)=0, [m] ([m]+1) affected flag(s) to pdf ov z ac c siza [m] increment data memory and place result in acc, skip if 0 description the contents of the specified data memory are incremented by 1. if the result is 0, the next instruction is skipped and the result is stored in the accumulator. the data memory re- mains unchanged. if the result is 0, the following instruction, fetched during the current in- struction execution, is discarded and a dummy cycle is replaced to get the proper instruction (2 cycles). otherwise proceed with the next instruction (1 cycle). operation skip if ([m]+1)=0, acc ([m]+1) affected flag(s) to pdf ov z ac c snz [m].i skip if bit i of the data memory is not 0 description if bit i of the specified data memory is not 0, the next instruction is skipped. if bit i of the data memory is not 0, the following instruction, fetched during the current instruction execution, is discarded and a dummy cycle is replaced to get the proper instruction (2 cycles). other - wise proceed with the next instruction (1 cycle). operation skip if [m].i 0 affected flag(s) to pdf ov z ac c HT23B60 rev. 1.10 45 march 1, 2004 sub a,[m] subtract data memory from the accumulator description the specified data memory is subtracted from the contents of the accumulator, leaving the result in the accumulator. operation acc acc+[m ]+1 affected flag(s) to pdf ov z ac c subm a,[m] subtract data memory from the accumulator description the specified data memory is subtracted from the contents of the accumulator, leaving the result in the data memory. operation [m] acc+[m ]+1 affected flag(s) to pdf ov z ac c sub a,x subtract immediate data from the accumulator description the immediate data specified by the code is subtracted from the contents of the accumula - tor, leaving the result in the accumulator. operation acc acc+x +1 affected flag(s) to pdf ov z ac c swap [m] swap nibbles within the data memory description the low-order and high-order nibbles of the specified data memory (1 of the data memo- ries) are interchanged. operation [m].3~[m].0 [m].7~[m].4 affected flag(s) to pdf ov z ac c swapa [m] swap data memory and place result in the accumulator description the low-order and high-order nibbles of the specified data memory are interchanged, writ - ing the result to the accumulator. the contents of the data memory remain unchanged. operation acc.3~acc.0 [m].7~[m].4 acc.7~acc.4 [m].3~[m].0 affected flag(s) to pdf ov z ac c HT23B60 rev. 1.10 46 march 1, 2004 sz [m] skip if data memory is 0 description if the contents of the specified data memory are 0, the following instruction, fetched during the current instruction execution, is discarded and a dummy cycle is replaced to get the proper instruction (2 cycles). otherwise proceed with the next instruction (1 cycle). operation skip if [m]=0 affected flag(s) to pdf ov z ac c sza [m] move data memory to acc, skip if 0 description the contents of the specified data memory are copied to the accumulator. if the contents is 0, the following instruction, fetched during the current instruction execution, is discarded and a dummy cycle is replaced to get the proper instruction (2 cycles). otherwise proceed with the next instruction (1 cycle). operation skip if [m]=0 affected flag(s) to pdf ov z ac c sz [m].i skip if bit i of the data memory is 0 description if bit i of the specified data memory is 0, the following instruction, fetched during the current instruction execution, is discarded and a dummy cycle is replaced to get the proper instruc - tion (2 cycles). otherwise proceed with the next instruction (1 cycle). operation skip if [m].i=0 affected flag(s) to pdf ov z ac c tabrdc [m] move the rom code (current page) to tblh and data memory description the low byte of rom code (current page) addressed by the table pointer (tblp) is moved to the specified data memory and the high byte transferred to tblh directly. operation [m] rom code (low byte) tblh rom code (high byte) affected flag(s) to pdf ov z ac c tabrdl [m] move the rom code (last page) to tblh and data memory description the low byte of rom code (last page) addressed by the table pointer (tblp) is moved to the data memory and the high byte transferred to tblh directly. operation [m] rom code (low byte) tblh rom code (high byte) affected flag(s) to pdf ov z ac c HT23B60 rev. 1.10 47 march 1, 2004 xor a,[m] logical xor accumulator with data memory description data in the accumulator and the indicated data memory perform a bitwise logical exclu - sive_or operation and the result is stored in the accumulator. operation acc acc xor [m] affected flag(s) to pdf ov z ac c xorm a,[m] logical xor data memory with the accumulator description data in the indicated data memory and the accumulator perform a bitwise logical exclu - sive_or operation. the result is stored in the data memory. the 0 flag is affected. operation [m] acc xor [m] affected flag(s) to pdf ov z ac c xor a,x logical xor immediate data to the accumulator description data in the accumulator and the specified data perform a bitwise logical exclusive_or op - eration. the result is stored in the accumulator. the 0 flag is affected. operation acc acc xor x affected flag(s) to pdf ov z ac c HT23B60 rev. 1.10 48 march 1, 2004 package information 100-pin qfp (14 20) outline dimensions symbol dimensions in mm min. nom. max. a 18.50 19.20 b 13.90 14.10 c 24.50 25.20 d 19.90 20.10 e 0.65 f 0.30 g 2.50 3.10 h 3.40 i 0.10 j1 1.40 k 0.10 0.20 0 7 HT23B60 rev. 1.10 49 march 1, 2004 ' & & * ' * & # ' # & ) ' ) & ' 3 6 4 + c ! HT23B60 rev. 1.10 50 march 1, 2004 copyright 2004 by holtek semiconductor inc. the information appearing in this data sheet is believed to be accurate at the time of publication. however, holtek as - sumes no responsibility arising from the use of the specifications described. the applications mentioned herein are used solely for the purpose of illustration and holtek makes no warranty or representation that such applications will be suitable without further modification, nor recommends the use of its products for application that may present a risk to human life due to malfunction or otherwise. holtek s products are not authorized for use as critical components in life support devices or systems. holtek reserves the right to alter its products without prior notification. for the most up-to-date information, please visit our web site at http://www.holtek.com.tw. holtek semiconductor inc. (headquarters) no.3, creation rd. ii, science park, hsinchu, taiwan tel: 886-3-563-1999 fax: 886-3-563-1189 http://www.holtek.com.tw holtek semiconductor inc. (taipei sales office) 4f-2, no. 3-2, yuanqu st., nankang software park, taipei 115, taiwan tel: 886-2-2655-7070 fax: 886-2-2655-7373 fax: 886-2-2655-7383 (international sales hotline) holtek semiconductor inc. (shanghai sales office) 7th floor, building 2, no.889, yi shan rd., shanghai, china 200233 tel: 021-6485-5560 fax: 021-6485-0313 http://www.holtek.com.cn holtek semiconductor inc. (shenzhen sales office) 43f, seg plaza, shen nan zhong road, shenzhen, china 518031 tel: 0755-8346-5589 fax: 0755-8346-5590 isdn: 0755-8346-5591 holtek semiconductor inc. (beijing sales office) suite 1721, jinyu tower, a129 west xuan wu men street, xicheng district, beijing, china 100031 tel: 010-6641-0030, 6641-7751, 6641-7752 fax: 010-6641-0125 holmate semiconductor, inc. (north america sales office) 46712 fremont blvd., fremont, ca 94538 tel: 510-252-9880 fax: 510-252-9885 http://www.holmate.com |
Price & Availability of HT23B60
 |
|
|
|
|
All Rights Reserved © IC-ON-LINE 2003 - 2022 |
| [Add Bookmark] [Contact Us] [Link exchange] [Privacy policy] |
|
Mirror Sites : [www.datasheet.hk]
[www.maxim4u.com] [www.ic-on-line.cn]
[www.ic-on-line.com] [www.ic-on-line.net]
[www.alldatasheet.com.cn]
[www.gdcy.com]
[www.gdcy.net] |